CPC G06F 30/398 (2020.01) [G03F 1/36 (2013.01); H01L 21/027 (2013.01); G06F 30/20 (2020.01); G06F 2119/18 (2020.01)] | 8 Claims |
1. A computing device, comprising:
a processor;
memory coupled to the processor, the memory storing computer-readable instructions that when executed by the processor, cause the processor to perform operations, the operations comprising:
decomposing a first layout of interest associated with an integrated circuit into a plurality of groups of layout patterns;
associating each of the groups of layout patterns with a canonically unique identifier so as to define a plurality of canonically unique identifiers;
storing the plurality of canonically unique identifiers in a pattern database so as to generate the pattern database;
decomposing a second layout of interest into layout sub-patterns;
identifying that at least one of the layout sub-patterns is associated with at least one of the plurality of groups of layout patterns;
identifying the canonically unique identifier for each of the identified layout sub-patterns associated with at least one of the plurality of groups of layout patterns;
using the canonically unique identifier for a respective identified layout sub-pattern, identifying a pattern defined by two or more of the layout sub-patterns associated with at least one of the plurality of groups of layout patterns, thereby performing puzzle matching;
determining a tolerance level defined by each of the identified layout sub-patterns; and
making a comparison of the respective tolerance levels to a predetermined tolerance, the predetermined tolerance indicative of whether the pattern matches a target layout.
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