US 11,704,460 B2
System and method for fast and accurate netlist to RTL reverse engineering
Yier Jin, Gainesville, FL (US); Shaojie Zhang, Orlando, FL (US); James Geist, Oviedo, FL (US); Travis Meade, Orlando, FL (US); and Jason Liam Portillo, San Jose, CA (US)
Assigned to UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED, Gainesville, FL (US)
Filed by University of Florida Research Foundation, Incorporated, Gainesville, FL (US); and University of Central Florida Research Foundation, Inc., Orlando, FL (US)
Filed on Jun. 9, 2021, as Appl. No. 17/343,231.
Claims priority of provisional application 63/037,073, filed on Jun. 10, 2020.
Prior Publication US 2021/0390236 A1, Dec. 16, 2021
Int. Cl. G06F 30/33 (2020.01); G06F 30/327 (2020.01); G06F 115/08 (2020.01)
CPC G06F 30/33 (2020.01) [G06F 30/327 (2020.01); G06F 2115/08 (2020.01)] 18 Claims
OG exemplary drawing
 
1. A method for reverse engineering of integrated circuits (ICs) for design verification, the method comprising:
receiving a gate-level netlist for an integrated circuit (IC), wherein the gate-level netlist comprises a description of connectivity for the integrated circuit and is formatted in a hardware description language;
generating, based at least in part on signals included in the gate-level netlist, a list of equivalence classes related to the signals;
determining, based at least in part on the list of equivalence classes, control signals of the gate-level netlist;
determining, based at least in part on the control signals, a logic flow of a finite state transducer (FST); and
generating, based at least in part on the FST, register transfer level (RTL) source code for the IC, wherein the RTL source code models the IC based on one or more of flow of signals between hardware components of the IC or logical operations associated with the signals.