US 11,704,260 B2
Memory controller
James A. Hall, Jr., Boise, ID (US); and Robert M. Walker, Raleigh, NC (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 5, 2020, as Appl. No. 16/809,791.
Application 16/809,791 is a division of application No. 15/623,514, filed on Jun. 15, 2017, granted, now 10,621,117.
Prior Publication US 2020/0201793 A1, Jun. 25, 2020
Int. Cl. G06F 3/06 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first memory device configured to support a first type of command;
a second memory device configured to support a second type of command; and
a host memory controller coupled to the first memory device and the second memory device via a channel, wherein the controller is configured to:
receive a first command of the first type of command;
select the first memory device that supports the first command;
select the first command for execution on the first memory device based on receiving the first type of command, wherein the first memory device is mapped to a range of addresses by the host memory controller and the second memory device acts as cache for the first memory device;
send a device select signal to the first memory device in response to selecting the first command for execution on the first memory device; and
send the first command to the first memory device.