US 11,704,256 B2
Facilitating sequential reads in memory sub-systems
Stephen Hanna, Fort Collins, CO (US); and Nadav Grosz, Broomfield, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 8, 2021, as Appl. No. 17/521,360.
Application 17/521,360 is a continuation of application No. 16/801,949, filed on Feb. 26, 2020, granted, now 11,200,179.
Prior Publication US 2022/0058138 A1, Feb. 24, 2022
Int. Cl. G06F 12/14 (2006.01); G06F 1/24 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 21/79 (2013.01); G06F 3/06 (2006.01)
CPC G06F 12/1458 (2013.01) [G06F 1/24 (2013.01); G06F 12/0246 (2013.01); G06F 12/06 (2013.01); G06F 12/1441 (2013.01); G06F 21/79 (2013.01); G06F 2212/7201 (2013.01); G06F 2221/2153 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A system comprising:
a memory component; and
a processing device, operatively coupled to the memory component, the processing device to perform operations comprising:
identifying an L2P record mapping a logical block address to a physical address of a memory block on the memory component;
determining a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record;
generating a token encoding the sequential assist value and a sub-region update count;
associating the token with the L2P record;
receiving, from a host system, a read command specifying the logical block address and the sequential assist value; and
reading, from the memory component, a plurality of memory blocks having consecutive physical addresses, wherein a number of the memory blocks is less than or equal to the sequential assist value.