US 11,704,253 B2
Performing speculative address translation in processor-based devices
Thomas Philip Speier, Wake Forest, NC (US); Jason S. Wohlgemuth, Seattle, WA (US); Artur Klauser, Seattle, WA (US); Gagan Gupta, Bellevue, WA (US); Cody D. Hartwig, Seattle, WA (US); and Abolade Gbadegesin, Sammamish, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Feb. 17, 2021, as Appl. No. 17/177,775.
Prior Publication US 2022/0261355 A1, Aug. 18, 2022
Int. Cl. G06F 9/38 (2018.01); G06F 12/1081 (2016.01); G06F 12/1036 (2016.01); G06F 9/30 (2018.01); G06F 9/455 (2018.01); G06F 11/07 (2006.01); G06F 12/0882 (2016.01); G06F 12/1045 (2016.01)
CPC G06F 12/1036 (2013.01) [G06F 9/3004 (2013.01); G06F 9/30079 (2013.01); G06F 9/30101 (2013.01); G06F 9/3842 (2013.01); G06F 9/45558 (2013.01); G06F 11/0772 (2013.01); G06F 12/0882 (2013.01); G06F 12/1054 (2013.01); G06F 12/1063 (2013.01); G06F 12/1081 (2013.01); G06F 2009/45583 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed by a processor-based device, cause the processor-based device to:
receive a memory-pointer-referencing (MPR) instruction that references a plurality of bytes that comprises a virtual memory address, wherein:
the MPR instruction comprises an enqueue instruction directed to a peripheral device; and
the virtual memory address comprises a virtual memory address to which the peripheral device will perform a Direct Memory Access (DMA) operation;
transmit, to a memory management unit (MMU) of the processor-based device, a request for address translation of the virtual memory address;
perform speculative address translation of the virtual memory address into a corresponding translated memory address, wherein computer-executable instructions cause the processor-based device to perform the speculative address translation by causing the processor-based device to perform one or more of a page table walk, an update of a translation table, and a caching of a result of the speculative address translation in a translation lookaside buffer (TLB); and
subsequent to the speculative address translation, execute the MPR instruction.