US 11,704,251 B2
Banked memory architecture for multiple parallel datapath channels in an accelerator
Stephen Sangho Youn, Bellevue, WA (US); Steven Karl Reinhardt, Vancouver, WA (US); and Hui Geng, Bellevue, WA (US)
Assigned to MICROSOFT TECHNOLOGY LICENSING, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Apr. 27, 2022, as Appl. No. 17/730,707.
Application 17/730,707 is a continuation of application No. 17/097,205, filed on Nov. 13, 2020, granted, now 11,347,652.
Claims priority of provisional application 63/072,427, filed on Aug. 31, 2020.
Prior Publication US 2022/0253384 A1, Aug. 11, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 12/00 (2006.01); G11C 7/10 (2006.01); G06F 12/0897 (2016.01); G11C 11/4076 (2006.01)
CPC G06F 12/0897 (2013.01) [G11C 7/1006 (2013.01); G11C 7/1057 (2013.01); G11C 7/1072 (2013.01); G11C 11/4076 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory architecture, comprising:
a plurality of memory banks;
a plurality of data channels, wherein each channel of the plurality of data channels is paired with a separate memory bank of the plurality of memory banks;
a switch in communication with the plurality of memory banks and the plurality of data channels, wherein the switch receives data and provides the data to the plurality of data channels; and
a scratchpad in communication with the switch, wherein the scratchpad identifies one memory bank of the plurality of memory banks as a multi-port memory bank.