CPC G06F 12/0897 (2013.01) [G11C 7/1006 (2013.01); G11C 7/1057 (2013.01); G11C 7/1072 (2013.01); G11C 11/4076 (2013.01)] | 15 Claims |
1. A memory architecture, comprising:
a plurality of memory banks;
a plurality of data channels, wherein each channel of the plurality of data channels is paired with a separate memory bank of the plurality of memory banks;
a switch in communication with the plurality of memory banks and the plurality of data channels, wherein the switch receives data and provides the data to the plurality of data channels; and
a scratchpad in communication with the switch, wherein the scratchpad identifies one memory bank of the plurality of memory banks as a multi-port memory bank.
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