| CPC G06F 11/3648 (2013.01) [G06F 8/40 (2013.01); G06F 8/73 (2013.01)] | 21 Claims |
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1. An apparatus comprising:
processor circuitry including one or more of:
at least one of a central processing unit, a graphic processing unit or a digital signal processor, the at least one of the central processing unit, the graphic processing unit or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations, the instructions in the apparatus;
a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations; or
Application Specific Integrated Circuitry (ASIC) including logic gate circuitry to perform one or more third operations;
the processor circuitry to perform at least one of the one or more first operations, the one or more second operations or the one or more third operations to instantiate:
repository interface circuitry to retrieve code repositories corresponding to a programming language of interest;
tree generating circuitry to generate parse trees corresponding to code blocks contained in the code repositories;
directed acyclic graph (DAG) circuitry to generate DAGs corresponding to respective ones of the parse trees, the DAGs including control flow information and data flow information;
abstraction generating circuitry to abstract the DAGs;
invariant identification circuitry to extract invariants from the abstracted DAGs; and
DAG comparison circuitry to cluster respective ones of the extracted invariants to identify respective ones of the abstracted DAGs with common invariants.
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