US 11,704,217 B2
Charge loss scan operation management in memory devices
Michael Sheperek, Longmont, CO (US); Steven Michael Kientz, Westminster, CO (US); Shane Nowell, Boise, ID (US); Mustafa N. Kaynak, San Diego, CA (US); Kishore Kumar Muchherla, Fremont, CA (US); and Larry J. Koudele, Erie, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 25, 2021, as Appl. No. 17/157,220.
Prior Publication US 2022/0237094 A1, Jul. 28, 2022
Int. Cl. G06F 11/30 (2006.01); G06F 3/06 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/3037 (2013.01) [G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0679 (2013.01); G06F 11/076 (2013.01); G06F 11/3058 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
identifying an operating temperature of the memory device;
identifying, for a set of blocks of the memory device, a scan frequency corresponding to the operating temperature, wherein the scan frequency exceeds one scan operation per a period of time in which the set of blocks stays associated with a certain threshold voltage offset;
responsive to determining that the operating temperature exceeds a threshold temperature, increasing the scan frequency; and
performing a scan operation with respect to a representative block of the set of blocks of the memory device at the scan frequency.