US 11,704,196 B2
Reduced parity data management
Chun Sum Yeung, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 4, 2022, as Appl. No. 17/712,978.
Application 17/712,978 is a continuation of application No. 17/004,136, filed on Aug. 27, 2020, granted, now 11,321,176.
Prior Publication US 2022/0229728 A1, Jul. 21, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/00 (2006.01); G06F 11/10 (2006.01); G11C 11/408 (2006.01); G06F 11/30 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1076 (2013.01) [G06F 11/0772 (2013.01); G06F 11/1068 (2013.01); G06F 11/3037 (2013.01); G11C 11/4085 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method, comprising:
generating parity data corresponding to a plurality of word lines coupled to respective blocks of a memory device;
dividing the parity data into one of either a first word line parity set or a second word line parity set by separating the parity data from even numbered word lines into the first word line parity set and separating the parity data from odd numbered word lines into the second word line parity set; and
generating a reduced parity data set for the first word line parity set and for the second word line parity set such that the reduced parity data set is stored within a quantity of word lines that is less than a total quantity of word lines among the plurality of word lines coupled to the respective blocks of the memory device.