CPC G06F 11/1068 (2013.01) [G06F 13/1668 (2013.01)] | 20 Claims |
1. A dynamic random access memory (DRAM) device, comprising:
a memory array to store data, wherein for a memory access operation, data bits and error checking and correction (ECC) bits are prefetched from the memory array; and
ECC hardware, internal to the DRAM device, to apply ECC, with a first group of a first half the data bits checked by a first half of the ECC bits, in parallel with a second group of a second half of the data bits checked by a second half of the ECC bits.
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