US 11,704,194 B2
Memory wordline isolation for improvement in reliability, availability, and scalability (RAS)
Kuljit S. Bains, Olympia, WA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 18, 2021, as Appl. No. 17/530,086.
Application 17/530,086 is a continuation of application No. 16/722,969, filed on Dec. 20, 2019, granted, now 11,210,167.
Claims priority of provisional application 62/927,116, filed on Oct. 28, 2019.
Prior Publication US 2022/0075689 A1, Mar. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 13/16 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 13/1668 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A dynamic random access memory (DRAM) device, comprising:
a memory array to store data, wherein for a memory access operation, data bits and error checking and correction (ECC) bits are prefetched from the memory array; and
ECC hardware, internal to the DRAM device, to apply ECC, with a first group of a first half the data bits checked by a first half of the ECC bits, in parallel with a second group of a second half of the data bits checked by a second half of the ECC bits.