CPC G06F 11/0772 (2013.01) [G06F 11/0727 (2013.01); G06F 11/0751 (2013.01); G06F 11/1004 (2013.01); G06F 11/1068 (2013.01); H03M 13/29 (2013.01)] | 20 Claims |
1. A data processor for providing memory commands to a memory channel according to predetermined criteria, comprising:
a first error code generation circuit for generating a first type of error code in response to data of a write request;
a second error code generation circuit for generating a second type of error code for said write request, said second type of error code different from said first type of error code; and
a queue coupled to said first error code generation circuit and to said second error code generation circuit, for providing write commands to an interface, said write commands including said data, said first type of error code, and said second type of error code.
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