US 11,704,183 B2
Data integrity for persistent memory systems and the like
Kedarnath Balakrishnan, Bangalore (IN); James R. Magro, Lakeway, TX (US); Kevin Michael Lepak, Austin, TX (US); and Vilas Sridharan, Brookline, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 7, 2021, as Appl. No. 17/544,074.
Application 17/544,074 is a continuation of application No. 16/705,913, filed on Dec. 6, 2019, granted, now 11,200,106.
Claims priority of application No. 201911032592 (IN), filed on Aug. 12, 2019.
Prior Publication US 2022/0091921 A1, Mar. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/07 (2006.01); H03M 13/29 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/0772 (2013.01) [G06F 11/0727 (2013.01); G06F 11/0751 (2013.01); G06F 11/1004 (2013.01); G06F 11/1068 (2013.01); H03M 13/29 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processor for providing memory commands to a memory channel according to predetermined criteria, comprising:
a first error code generation circuit for generating a first type of error code in response to data of a write request;
a second error code generation circuit for generating a second type of error code for said write request, said second type of error code different from said first type of error code; and
a queue coupled to said first error code generation circuit and to said second error code generation circuit, for providing write commands to an interface, said write commands including said data, said first type of error code, and said second type of error code.