US 11,704,155 B2
Heterogeneous system on a chip scheduler
Augusto Vega, Mount Vernon, NY (US); Alper Buyuktosunoglu, White Plains, NY (US); Hubertus Franke, Cortlandt Manor, NY (US); John-David Wellman, Hopewell Junction, NY (US); Pradip Bose, Yorktown Heights, NY (US); Robert Matthew Senger, Tarrytown, NY (US); and Aporva Amarnath, Ann Arbor, MI (US)
Assigned to International Business Machine Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jul. 1, 2020, as Appl. No. 16/917,975.
Prior Publication US 2022/0004433 A1, Jan. 6, 2022
Int. Cl. G06F 9/48 (2006.01); G06Q 20/14 (2012.01); G06F 16/901 (2019.01)
CPC G06F 9/4893 (2013.01) [G06F 16/9024 (2019.01); G06Q 20/145 (2013.01); G06F 2209/486 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous system on a chip (SoC) and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC;
determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph;
providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank;
executing, by the heterogenous SoC, the respective task according to the rank;
determining that respective priorities of additional tasks in the directed acyclic graph are non-critical;
determining that an updated slack in the directed acyclic graph is negative;
canceling the additional tasks in the directed acyclic graph; and
proceeding to a next directed acyclic graph.