US 11,704,092 B2
High-precision anchored-implicit processing
Neil Burgess, Cardiff (GB); Christopher Neal Hinds, Austin, TX (US); David Raymond Lutz, Austin, TX (US); and Pedro Olsen Ferreira, Harlow (GB)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Oct. 27, 2020, as Appl. No. 17/81,068.
Prior Publication US 2022/0129245 A1, Apr. 28, 2022
Int. Cl. G06F 7/509 (2006.01); G06F 7/499 (2006.01); G06F 7/487 (2006.01)
CPC G06F 7/49947 (2013.01) [G06F 7/487 (2013.01); G06F 7/509 (2013.01); G06F 2207/3808 (2013.01); G06F 2207/3832 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a processing circuit configured to perform one or more processing operations in response to one or more instructions to generate a plurality of anchored-data elements, generate a result value by accumulating a plurality of respective data values in the plurality of anchored-data elements, and alter a lane identification value for the result value automatically during the accumulation; and
a storage device configured to store each respective anchored-data element of the plurality of anchored-data elements in a respective single register, wherein:
a format of each respective anchored-data element of the plurality of anchored-data elements includes an identification item, an overlap item, and a data item;
the data item is configured to hold the respective data value of the respective anchored-data element of the plurality of anchored-data elements;
the identification item includes a lane item and a special item; and
the special items indicates that the lane item contains one of (i) the lane identification value and (ii) one of a plurality of special values; and
wherein the result value has the format of the plurality of anchored-data elements.