US 11,704,070 B2
Managed NAND data compression
Sebastien Andre Jean, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 11, 2022, as Appl. No. 17/692,732.
Application 17/692,732 is a division of application No. 17/084,289, filed on Oct. 29, 2020, granted, now 11,288,016.
Application 17/084,289 is a continuation of application No. 16/012,750, filed on Jun. 19, 2018, granted, now 10,824,371.
Claims priority of provisional application 62/521,939, filed on Jun. 19, 2017.
Prior Publication US 2022/0197566 A1, Jun. 23, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/064 (2013.01); G06F 3/0604 (2013.01); G06F 3/068 (2013.01); G06F 3/0608 (2013.01); G06F 3/0611 (2013.01); G06F 3/0647 (2013.01); G06F 3/0649 (2013.01); G06F 3/0661 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a host device comprising a host processor and a group of volatile memory cells; and
a single storage system comprising a group of non-volatile memory cells and a storage system processor,
wherein the storage system processor is configured to:
provide available data operations for the storage system processor to the host processor, and
wherein the host processor is configured to:
identify data operations to be performed by the storage system processor; and
assign identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.