US 11,704,061 B2
Page buffer enhancements
Neil Buxton, Berkshire (GB); Avadhani Shridhar, San Jose, CA (US); Steven Wells, Rancho Cordova, CA (US); and Nicole Ross, Folsom, CA (US)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Minato (JP)
Filed on Mar. 16, 2021, as Appl. No. 17/203,392.
Prior Publication US 2022/0300199 A1, Sep. 22, 2022
Int. Cl. G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 11/56 (2013.01)] 39 Claims
OG exemplary drawing
 
1. A memory storage system comprising:
a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers; and
a controller in communication with the plurality of buffers, and configured to issue a first command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers, the data payload to be encoded by the non-volatile semiconductor memory device,
wherein the controller is further configured to issue a second command to the non-volatile semiconductor memory device to cause the data payload in the subset of n first buffers to be encoded in n second buffers of the plurality of buffers separate from the n first buffers, and stored in the memory array.