US 11,704,060 B2
Split protocol approaches for enabling devices with enhanced persistent memory region access
Luca Bert, San Jose, CA (US); and Joseph H. Steinmetz, Loomis, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 13, 2021, as Appl. No. 17/147,834.
Claims priority of provisional application 63/127,213, filed on Dec. 18, 2020.
Prior Publication US 2022/0197556 A1, Jun. 23, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, by a processor, a host command to configure a system to have a configuration designating a first interface standard at a first port for exposing a storage element and a second interface standard implementing compute express link (CXL) at a second port for exposing a persistent memory region (PMR), the storage element being implemented on a non-volatile memory device of the system and the PMR being implemented on a volatile memory device of the system as a power protected region of the volatile memory device, wherein the second interface standard is different from the first interface standard, wherein the first interface standard supports one or more alternate protocols implemented by the second interface standard, and wherein the system is operatively coupled to a first switch for implementing the first interface standard and a second switch for implementing the second interface standard; and
configuring, by the processor, the system in accordance with the configuration, including:
exposing the storage element by designating the first interface standard at the first port;
exposing the PMR by designating the second interface standard at the second port; and
allocating a segment of the PMR as a cacheable memory marked as visible through the second interface standard, wherein the segment of the PMR is detected as an internal memory range that is shared through the second interface standard.