US 11,704,057 B2
Memory sub-systems including memory devices of various latencies and capacities
Luca Bert, Milpitas, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 20, 2020, as Appl. No. 16/933,755.
Prior Publication US 2022/0019379 A1, Jan. 20, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 12/1009 (2016.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 12/1009 (2013.01); G06F 2212/657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of memory devices; and
a processing device, operatively coupled with the plurality of memory devices, to perform operations comprising:
receiving a write command comprising a logical address, a payload, and an indicator reflecting a functional characteristic of the payload, wherein the functional characteristic is selected from a group consisting of a key and a value associated with a key-value store;
identifying, based on the indicator, a value of a parameter associated with storing the payload on one or more of the plurality of memory devices;
determining that the value of the parameter satisfies a criterion associated with a particular memory device of the plurality of memory devices; and
storing the payload on the particular memory device.