US 11,704,032 B2
Switchable lane directions between a host system and a memory system
Christian M. Gyllenskog, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 26, 2021, as Appl. No. 17/240,927.
Prior Publication US 2022/0342572 A1, Oct. 27, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0635 (2013.01) [G06F 3/0613 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 16 Claims
OG exemplary drawing
 
13. An apparatus, comprising:
a memory system comprising a memory system controller; and
a link comprising a first lane, the link being between the memory system controller and a host system controller, wherein the first lane is configurable to send information to the host system controller based at least in part on activating a transmit module at the memory system controller and is configurable to receive information from the host system controller based at least in part on activating a receive module at the memory system controller, wherein the memory system controller comprises logic configured to send a ready to transfer (RTT) universal flash storage (UFS) protocol information unit (UPIU) to reconfigure the first lane to support additional bandwidth in a first direction or a second direction.