US 11,704,029 B2
Elastic persistent memory regions
Joseph H. Steinmetz, Loomis, CA (US); Luca Bert, San Jose, CA (US); and William Akin, Morgan Hill, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 16, 2021, as Appl. No. 17/232,971.
Prior Publication US 2022/0334740 A1, Oct. 20, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 12/0808 (2016.01)
CPC G06F 3/0631 (2013.01) [G06F 3/0604 (2013.01); G06F 3/068 (2013.01); G06F 3/0644 (2013.01); G06F 12/0808 (2013.01); G06F 2212/1044 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system comprising:
a volatile memory device having a power protected region allocated as a first persistent memory region (PMR) having a first set of pages, wherein the power protected region utilizes a mechanism to, in an event of power loss, provide power to enable writes of data from the volatile memory device to non-volatile memory;
a non-volatile memory device having a region allocated as a second PMR having a second set of pages; and
at least one processing device, operatively coupled to the volatile memory device and the non-volatile memory device, to perform operations comprising:
causing the second PMR to be accessible through the first PMR.