US 11,704,028 B2
Asynchronous power loss impacted data structure
Xiangang Luo, Fremont, CA (US); Ting Luo, Santa Clara, CA (US); and Jianmin Huang, San Carlos, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 11, 2022, as Appl. No. 17/692,683.
Application 17/692,683 is a continuation of application No. 16/406,627, filed on May 8, 2019, granted, now 11,275,512.
Claims priority of provisional application 62/668,713, filed on May 8, 2018.
Prior Publication US 2022/0197517 A1, Jun. 23, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01); G11C 16/34 (2006.01); G06F 1/3206 (2019.01)
CPC G06F 3/0619 (2013.01) [G06F 1/3206 (2013.01); G06F 3/0647 (2013.01); G06F 3/0685 (2013.01); G06F 11/076 (2013.01); G06F 11/1471 (2013.01); G11C 16/3404 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a storage system comprising control circuitry and a memory array having multiple groups of memory cells,
wherein the control circuitry is configured to maintain a relationship between a logical block address (LBA) and a physical address (PA) of data stored on the memory array in a logical-to-physical (L2P) data structure and store a synchronization point indicating a specific point where data operations on the memory array are complete and the L2P data is updated and stored, and
wherein the control circuitry, when resuming operation from a low-power state, is configured to:
determine an error rate of one or more groups of memory cells programmed or erased subsequent to the synchronization point;
relocate groups of memory cells having an error rate above a stable threshold;
rebuild the L2P data structure subsequent to relocating the groups of memory cells having the error rate above the stable threshold;
update the synchronization point subsequent to rebuilding the L2P data structure; and
transition from resuming operation from the low-power state to in operation subsequent to updating the synchronization point,
wherein the stable threshold is below and separate from a maximum error threshold, wherein the maximum error threshold is a threshold above which the system is not configured to correct errors in the group of memory cells.