CPC G06F 3/0619 (2013.01) [G06F 1/3206 (2013.01); G06F 3/0647 (2013.01); G06F 3/0685 (2013.01); G06F 11/076 (2013.01); G06F 11/1471 (2013.01); G11C 16/3404 (2013.01)] | 20 Claims |
1. A system comprising:
a storage system comprising control circuitry and a memory array having multiple groups of memory cells,
wherein the control circuitry is configured to maintain a relationship between a logical block address (LBA) and a physical address (PA) of data stored on the memory array in a logical-to-physical (L2P) data structure and store a synchronization point indicating a specific point where data operations on the memory array are complete and the L2P data is updated and stored, and
wherein the control circuitry, when resuming operation from a low-power state, is configured to:
determine an error rate of one or more groups of memory cells programmed or erased subsequent to the synchronization point;
relocate groups of memory cells having an error rate above a stable threshold;
rebuild the L2P data structure subsequent to relocating the groups of memory cells having the error rate above the stable threshold;
update the synchronization point subsequent to rebuilding the L2P data structure; and
transition from resuming operation from the low-power state to in operation subsequent to updating the synchronization point,
wherein the stable threshold is below and separate from a maximum error threshold, wherein the maximum error threshold is a threshold above which the system is not configured to correct errors in the group of memory cells.
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