US 11,704,019 B2
Memory system, host device and information processing system for error correction processing
Shinichi Kanno, Tokyo (JP); Hiroshi Nishimura, Hachioji Tokyo (JP); Hideki Yoshida, Yokohama Kanagawa (JP); and Hiroshi Murayama, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Oct. 23, 2020, as Appl. No. 17/78,547.
Application 17/078,547 is a continuation of application No. 15/632,450, filed on Jun. 26, 2017, granted, now 10,866,733.
Application 15/632,450 is a continuation of application No. 14/817,625, filed on Aug. 4, 2015, abandoned.
Claims priority of provisional application 62/035,243, filed on Aug. 8, 2014.
Prior Publication US 2021/0042033 A1, Feb. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 1/3234 (2019.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); H03M 13/29 (2006.01); G06F 12/02 (2006.01); G11C 16/24 (2006.01); G11C 16/04 (2006.01)
CPC G06F 3/0604 (2013.01) [G06F 1/3275 (2013.01); G06F 3/0619 (2013.01); G06F 3/0653 (2013.01); G06F 3/0655 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 3/0688 (2013.01); G06F 11/1068 (2013.01); G11C 29/52 (2013.01); H03M 13/2906 (2013.01); G06F 12/0246 (2013.01); G06F 2212/214 (2013.01); G11C 16/0483 (2013.01); G11C 16/24 (2013.01); Y02D 10/00 (2018.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a nonvolatile memory;
a first decoder configured to execute a first error correction for correcting data read from the nonvolatile memory;
a second decoder configured to execute a second error correction for correcting data read from the nonvolatile memory, an acceptable latency of the second error correction being different from that of the first error correction; and
a controller configured to
receive a first command issued by a host device, the first command being a command that requests neither reading nor writing data from or to the nonvolatile memory and that includes information indicative of acceptable latency of error correction,
in response to receiving the first command, select one of the first decoder and the second decoder based on the received first command,
receive a second command issued by the host device, the second command being a command that requests reading data from the non-volatile memory, and
after receiving the first command, output the data read from the nonvolatile memory through the selected one of the first decoder and the second decoder to the host device.