| CPC G06F 1/08 (2013.01) [G06F 1/3203 (2013.01); G06F 1/324 (2013.01); G06F 9/30101 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45591 (2013.01)] | 26 Claims |
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1. A multi-core processor comprising:
a plurality of control registers, each control register of the plurality of control registers associated with a corresponding processing core;
the plurality of control registers to store a corresponding plurality of values to indicate a per-core clock frequency for the corresponding processing cores, the plurality of values initially comprising a plurality of default values to indicate a default per-core clock frequency for the corresponding processing core, the plurality of default values determined during manufacture of the multi-core processor; and
power management circuitry to execute power management firmware to control clock frequencies of the processing cores based, at least in part, on the plurality of values, the power management circuitry to:
receive a plurality of requested values different from corresponding default values of the plurality of default values;
store the plurality of requested values in corresponding control registers of the plurality of control registers, the requested values to indicate a requested per-core clock frequency for the corresponding processing core of the processing cores;
cause each corresponding processing core of the processing cores to run at the corresponding requested per-core clock frequency; and
expose the requested values to software.
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