US 11,703,542 B2
Embedded test apparatus for high speed interfaces
Dietmar Koenig, Munich (DE); and Hosea Busse, Jena (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Feb. 28, 2022, as Appl. No. 17/681,970.
Claims priority of application No. 10 2021 001 093.0 (DE), filed on Mar. 1, 2021.
Prior Publication US 2022/0276305 A1, Sep. 1, 2022
Int. Cl. G01R 31/317 (2006.01); G01R 31/3187 (2006.01)
CPC G01R 31/31721 (2013.01) [G01R 31/3187 (2013.01)] 20 Claims
OG exemplary drawing
 
7. A method for testing an integrated circuit, whereby the method comprises:
receiving an input signal at a receive unit to be tested, and storing the input signal at a predetermined point in time;
providing a filtered input signal based on the input signal;
applying an error correction to the input signal, thereby generating an error corrected signal;
comparing the error corrected signal with an expectation value;
outputting an error message when the filtered input signal does not correspond to the expectation value;
supplying the receive unit to be tested with an adjustable voltage or an adjustable current; and
varying the predetermined point in time and the adjustable voltage or the adjustable current.