US 11,703,526 B2
Power failure detection circuit
Toby Bao, Guangdong (CN)
Assigned to XTX Technology Inc., Shenzhen (CN)
Appl. No. 17/295,548
Filed by XTX Technology Inc., Guangdong (CN)
PCT Filed Nov. 11, 2020, PCT No. PCT/CN2020/128138
§ 371(c)(1), (2) Date May 20, 2021,
PCT Pub. No. WO2021/135661, PCT Pub. Date Jul. 8, 2021.
Claims priority of application No. 201911389778.5 (CN), filed on Dec. 30, 2019.
Prior Publication US 2022/0308098 A1, Sep. 29, 2022
Int. Cl. G01R 19/165 (2006.01); G01R 31/52 (2020.01); G01R 19/145 (2006.01); G01R 31/40 (2020.01)
CPC G01R 19/16519 (2013.01) [G01R 19/145 (2013.01); G01R 19/16552 (2013.01); G01R 31/40 (2013.01); G01R 31/52 (2020.01)] 4 Claims
OG exemplary drawing
 
1. A power failure detection circuit, comprising a first PMOS FET (mp1), a second PMOS PET (mp2), a first NMOS FET (mn2), a second NMOS PET (mn3) and a reset transistor (mn1), wherein the source electrode of the first PMOS FET (mp1) is connected with a power supply terminal (VCC), the gate electrode of the first PMOS FET (mp1) is connected with the drain electrode of the second PMOS FET (mp2), and the drain electrode of the first PMOS FET (mp1) is connected with the drain electrode of the first NMOS PET (mn2); the source electrode of the second PMOS FET (mp2) is connected with the power supply terminal (VCC), the gate electrode of the second PMOS FET (mp2) is connected with the drain electrode of the first PMOS FET (mp1), and the drain electrode of the second PMOS FET (mp2) is connected with the drain electrode of the second NMOS FET (mn3); the gate electrode of the first NMOS FET (mn2) is connected with the drain electrode of the second NMOS FET (mn3); the source electrode of the first NMOS FET (mn2) is grounded; the gate electrode of the second NMOS FET (mn3) is connected with the drain electrode of the first NMOS PET (mn2), and the source electrode of the second NMOS FET (mn3) is grounded;
the PN junction area of the drain electrode of the first PMOS PET (mp1) is greater than the PN junction area of the drain electrode of the first NMOS FET (mn2); the PN junction area of the drain electrode of the second NMOS FET (mn3) is greater than the PN junction area of the drain electrode of the second PMOS FET (mp2); and a current electrode of the reset transistor (mn1) is electrically connected with the drain electrode of the first PMOS FET (mp1) to output a reset electrical signal.