US 10,716,209 B2
Fiber weave-sandwiched differential pair routing technique
Bok Eng Cheah, Bukit Gambir (MY); Eng Huat Goh, Penang (MY); Jackson Chung Peng Kong, Tanjung Tokong (MY); Khang Choong Yong, Puchong (MY); and Min Suet Lim, Simpang Ampat (MY)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 10, 2019, as Appl. No. 16/565,639.
Claims priority of application No. 2018704002 (MY), filed on Oct. 29, 2018.
Prior Publication US 2020/0137886 A1, Apr. 30, 2020
Int. Cl. H05K 1/11 (2006.01); H05K 3/40 (2006.01); H05K 1/03 (2006.01); H05K 3/46 (2006.01)
CPC H05K 1/036 (2013.01) [H05K 1/115 (2013.01); H05K 3/4038 (2013.01); H05K 3/4673 (2013.01); H05K 2201/029 (2013.01); H05K 2201/09563 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A printed circuit board, comprising:
a central dielectric layer including at least one fiber that provides mechanical strength for the printed circuit board;
a top dielectric layer disposed above the central dielectric layer;
a top electrical trace layer positioned between the central dielectric layer and the top dielectric layer, top electrical trace layer being patterned to form a top electrical trace having longitudinal ends that electrically connect through the top dielectric layer by electrically conductive vias; and
a bottom electrical trace layer positioned below the central dielectric layer, the bottom electrical trace layer being patterned to form a bottom electrical trace having longitudinal ends that each electrically connect through the central and top dielectric layers by electrically conductive vias, at least a portion of the bottom electrical trace being parallel to and directly below at least a portion of the top electrical trace.