CPC H10B 61/10 (2023.02) [G06N 3/02 (2013.01); G11C 11/165 (2013.01); H10N 50/10 (2023.02)] | 20 Claims |
1. A two-terminal multi-level memristor comprising:
a first set of resistance elements comprising a plurality of resistance elements connected in series between first and second terminals of the multi-level memristor; and
a second set of resistance elements comprising a plurality of second resistance elements, wherein each of the resistance elements of the second set is connected in parallel with a different number of one or more of the series connected resistance elements of the first set,
wherein one of the first set and second set of resistance elements comprises a plurality of binary memristors that can be selectively programmed to either a high or low resistance state and the other of the first and second set of resistance elements comprises a plurality of shunt resistors.
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