US 11,696,452 B2
Multi-level memristor elements
John Paul Lesso, Edinburgh (GB); and Gordon James Bates, Edinburgh (GB)
Assigned to Cirrus Logic, Inc., Austin, TX (US)
Filed by Cirrus Logic International Semiconductor Ltd., Edinburgh (GB)
Filed on May 5, 2021, as Appl. No. 17/308,695.
Application 17/308,695 is a continuation of application No. 16/781,157, filed on Feb. 4, 2020, granted, now 11,018,186.
Claims priority of provisional application 62/801,895, filed on Feb. 6, 2019.
Claims priority of application No. 1907685 (GB), filed on May 30, 2019.
Prior Publication US 2021/0257405 A1, Aug. 19, 2021
Int. Cl. G11C 11/00 (2006.01); H10B 61/00 (2023.01); G06N 3/02 (2006.01); G11C 11/16 (2006.01); H10N 50/10 (2023.01)
CPC H10B 61/10 (2023.02) [G06N 3/02 (2013.01); G11C 11/165 (2013.01); H10N 50/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A two-terminal multi-level memristor comprising:
a first set of resistance elements comprising a plurality of resistance elements connected in series between first and second terminals of the multi-level memristor; and
a second set of resistance elements comprising a plurality of second resistance elements, wherein each of the resistance elements of the second set is connected in parallel with a different number of one or more of the series connected resistance elements of the first set,
wherein one of the first set and second set of resistance elements comprises a plurality of binary memristors that can be selectively programmed to either a high or low resistance state and the other of the first and second set of resistance elements comprises a plurality of shunt resistors.