CPC H10B 41/20 (2023.02) [G11C 7/18 (2013.01); G11C 8/14 (2013.01); H10B 41/10 (2023.02)] | 15 Claims |
9. A cell array in a nonvolatile memory device, the cell array comprising:
first floating gates disposed in a first row on a substrate;
second floating gates disposed in a second row;
a first control gate surrounding the first floating gates, the first control gate comprising first sub-control gates connected to each other, and each of the first sub-control gates being tilted positively with respect to an X-axis; and
a second control gate surrounding the second floating gates, the second control gate comprising second sub-control gates connected to each other, and each of the second sub-control gates being tilted negatively with respect to the X-axis.
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