| CPC H10B 20/20 (2023.02) [G06F 30/392 (2020.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01)] | 20 Claims |
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1. An integrated circuit (IC) device comprising:
first through third device pairs positioned in corresponding first through third active areas extending in a first direction, wherein
each device pair comprises a first transistor coupled between a first anti-fuse structure and a shared bit line contact, and a second transistor coupled between a second anti-fuse structure and the shared bit line contact, and
each of the first and third active areas is adjacent to the second active area along a second direction perpendicular to the first direction;
first through fourth conductive lines extending in the second direction;
first and second conductive paths, each configured to couple the first conductive line to the first anti-fuse structure of each device pair;
a third conductive path configured to couple the fourth conductive line to the second anti-fuse structure of each device pair; and
a fourth conductive path configured to couple the third conductive line to the second transistor of each device pair,
wherein
the first and third conductive paths are aligned with each other along the first direction and positioned between the first and second active areas, and
the second and fourth conductive paths are aligned with each other along the first direction and positioned between the second and third active areas.
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