US 11,696,435 B2
Semiconductor memory structure and method for forming the same
Jiun-Sheng Yang, Taichung (TW); and Hsing-Hao Chen, Kaohsiung (TW)
Assigned to WINBOND ELECTRONICS CORP., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Aug. 13, 2021, as Appl. No. 17/402,087.
Claims priority of application No. 110100824 (TW), filed on Jan. 8, 2021.
Prior Publication US 2022/0223599 A1, Jul. 14, 2022
Int. Cl. H01B 12/00 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/315 (2023.02) [H10B 12/482 (2023.02); H10B 12/488 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor memory structure, comprising:
providing a semiconductor substrate, wherein a pair of word lines is embedded in an active region of the semiconductor substrate and extends in a first direction;
forming a hard mask layer on the semiconductor substrate;
forming a contact opening corresponding to the pair of word lines through the hard mask layer and a portion of the semiconductor substrate;
forming a pair of spacers on sidewalls of the contact opening;
filling the contact opening with a conductive material to form a contact;
planarizing a portion of the hard mask layer and the conductive material to be coplanar after the step of filling the conductive material, wherein a remaining of the conductive material acts as the contact and a remaining of the hard mask layer acts as a cap layer;
forming a bit line directly above the contact and the pair of spacers after the step of planarizing, wherein the bit line extends in a second direction that is perpendicular to the first direction; and
forming a dielectric liner on sidewalls of the bit line.