US 11,696,229 B2
Power saving mechanism for MU-MIMO transmissions
Ou Yang, Santa Clara, CA (US); Carlos Cordeiro, Portland, OR (US); Laurent Cariou, Portland, OR (US); Chittabrata Ghosh, Fremont, CA (US); and Solomon Trainin, Haifa (IL)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Sep. 7, 2021, as Appl. No. 17/468,289.
Application 17/468,289 is a continuation of application No. 16/786,638, filed on Feb. 10, 2020, granted, now 11,115,925.
Application 16/786,638 is a continuation of application No. 15/712,101, filed on Sep. 21, 2017, granted, now 10,568,027, issued on Feb. 18, 2020.
Application 15/712,101 is a continuation of application No. 15/390,376, filed on Dec. 23, 2016, granted, now 9,794,879, issued on Oct. 17, 2017.
Prior Publication US 2021/0410064 A1, Dec. 30, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H04B 1/38 (2015.01); H04W 52/02 (2009.01); H04B 7/0452 (2017.01)
CPC H04W 52/0216 (2013.01) [H04B 7/0452 (2013.01); H04W 52/0219 (2013.01); Y02D 30/70 (2020.08)] 26 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory of a first station (STA); and
processing circuitry of the first STA coupled to the memory, the processing circuitry to:
generate a first multiple-user PHY protocol data unit (MU-PPDU) to communicate in a downlink (DL) multiple-user multiple-input and multiple-output (MU-MIMO) communication to initiate a reverse direction (RD) communication, the MU-PPDU comprising aggregated frames, the aggregated frames comprising a frame to request a block acknowledgement and a quality of service (QoS) frame comprising a grant for a RD communication;
cause transmission of the first MU-PPDU to a second STA;
process the reverse direction communication including a first block acknowledgement and data in response to the first MU-PPDU; and
cause transmission of a second block acknowledgement to acknowledge the reverse direction communication.