CPC H04W 52/0216 (2013.01) [H04B 7/0452 (2013.01); H04W 52/0219 (2013.01); Y02D 30/70 (2020.08)] | 26 Claims |
1. An apparatus, comprising:
a memory of a first station (STA); and
processing circuitry of the first STA coupled to the memory, the processing circuitry to:
generate a first multiple-user PHY protocol data unit (MU-PPDU) to communicate in a downlink (DL) multiple-user multiple-input and multiple-output (MU-MIMO) communication to initiate a reverse direction (RD) communication, the MU-PPDU comprising aggregated frames, the aggregated frames comprising a frame to request a block acknowledgement and a quality of service (QoS) frame comprising a grant for a RD communication;
cause transmission of the first MU-PPDU to a second STA;
process the reverse direction communication including a first block acknowledgement and data in response to the first MU-PPDU; and
cause transmission of a second block acknowledgement to acknowledge the reverse direction communication.
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