CPC H04N 19/11 (2014.11) [H04N 19/105 (2014.11); H04N 19/132 (2014.11); H04N 19/159 (2014.11); H04N 19/176 (2014.11)] | 23 Claims |
1. A coding apparatus, comprising:
a memory storing instructions; and
one or more processors coupled to the memory, the one or more processors configured to execute the instructions to cause the coding apparatus to:
select an intra prediction mode for a current block; and
encode the selected intra prediction mode using truncated binary coding every time the selected intra prediction mode is a remaining mode, wherein the encoding the selected intra prediction mode comprises using N bits when the selected intra prediction mode is included in a first portion from remaining modes and using N+1 bits when the selected intra prediction mode is included in a second portion of the remaining modes.
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