CPC H04N 19/103 (2014.11) [H04N 19/176 (2014.11); H04N 19/61 (2014.11)] | 18 Claims |
1. An apparatus for image decoding, the apparatus comprising:
memory storing instructions that, when executed, cause one or more processors to perform operations comprising:
obtaining prediction mode information and residual related information from a bitstream,
deriving prediction mode for a current block based on the prediction mode information,
deriving prediction samples of the current block based on the prediction mode, deriving residual samples of the current block based on the residual related information, and
generating reconstruction samples of the current block based on the prediction samples and the residual samples,
wherein the prediction mode information is related to whether inter prediction or intra prediction is applied to the current block,
wherein the residual related information comprises a transform skip flag based on a size of the current block and a maximum transform skip size, wherein the transform skip flag is related to whether a transform skip is applied to the current block,
wherein information about the maximum transform skip size is obtained from the bitstream,
wherein the information about the maximum transform skip size includes a log 2_transform_skip_max_size_minus2 syntax element, and
wherein the maximum transform skip size is derived based on the following equation,
where the MaxTsSize represents the maximum transform skip size, and the log 2_transform_skip_max_size_minus2 represents a value of the log 2_transform_skip_max_size_minus2 syntax element.
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