CPC H04L 67/568 (2022.05) [G06F 11/1464 (2013.01); G06F 11/1474 (2013.01); G06Q 40/04 (2013.01); H04L 12/00 (2013.01); H04L 67/55 (2022.05); G06F 2201/805 (2013.01); G06F 2201/84 (2013.01)] | 25 Claims |
1. A system comprising:
a processor configured to:
repeatedly receive, and accumulate in a memory coupled with the processor, a variable amount of data during a determined variable length interval for encoding and transmission subsequent to an end thereof, a length of each variable length interval being determined based on an amount of time needed to encode the accumulated received data and an amount of time needed to transmit, via an electronic communications network to a recipient, previously encoded data accumulated during a prior interval such that the encoding of the accumulated data is completed upon the completion of the transmission of the previously encoded data; and
commence encoding, subsequent to the end of the determined variable length interval, the accumulated received data, the transmission thereof and encoding of subsequently accumulated data being able to commence once the accumulated received data has been encoded.
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