CPC H04L 25/4906 (2013.01) [H03M 3/424 (2013.01); H03M 3/43 (2013.01); H03M 3/496 (2013.01); H04B 1/0007 (2013.01); H04W 88/085 (2013.01); H04B 10/2575 (2013.01)] | 20 Claims |
1. A delta-sigma digitization interface for digitizing an input analog signal into a digitized bit stream, comprising: a sampling unit configured to sample the input analog signal at a predetermined sampling rate to produce a sampled analog signal; a segmentation unit configured to segment the sampled analog signal into a plurality of separate data pipelines; a delta-sigma analog-to-digital converter (ADC) having a processor and a memory, and wherein the memory contains computer-executable instructions that, when executed by the processor, cause the delta-sigma ADC to implement a delta-sigma algorithm configured to individually quantize a respective signal segment contained within each of the plurality of data pipelines into a digitized bit stream segment according to a predetermined number of quantization bits; a cascading unit configured to combine the respective quantized signal segments into a single digitized output stream; and an output port for transmitting the single digitized output stream to a transport medium as the digitized bit stream.
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8. A delta-sigma digitization interface for digitizing an input analog signal into a digitized bit stream, comprising: a sampling unit configured to sample the input analog signal at a predetermined sampling rate to produce a sampled analog signal; a segmentation unit configured to segment and distribute contiguous data portions of the sampled analog signal in sequential order into a plurality of separate data pipelines, respectively; a delta-sigma analog-to-digital converter (ADC) configured to individually quantize a respective data portion contained within each of the plurality of data pipelines into a digitized bit stream segment according to a predetermined number of quantization bits; a cascading unit configured to combine the respective quantized signal segments into a single digitized output stream; and an output port for transmitting the single digitized output stream to a transport medium as the digitized bit stream.
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18. A method of optimizing a delta-sigma analog-to-digital converter (ADC) architecture for a field programmable gate array (FPGA), comprising the steps of: simulating a performance of the delta-sigma ADC according to a first floating-point calculation using floating-point coefficients of the delta-sigma ADC; approximating key coefficients from a floating-point format to a fixed-point format; performing a second floating-point calculation of the delta-sigma ADC performance using the approximated key fixed-point coefficients; performing a first fixed-point calculation of the delta-sigma ADC performance for a continuous input data stream using fixed-point coefficients obtained from performance of the second floating-point calculation; and performing a second fixed-point calculation of the delta-sigma ADC performance, wherein the continuous input data stream is segmented into a plurality of separate data blocks, and wherein the second fixed-point calculation is individually performed on each separate segmented data block.
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