US 11,695,599 B1
Systems and methods for delta-sigma digitization
Jing Wang, Broomfield, CO (US); Luis Alberto Campos, Superior, CO (US); and Zhensheng Jia, Superior, CO (US)
Assigned to Cable Television Laboratories, Inc., Louisville, CO (US)
Filed by CABLE TELEVISION LABORATORIES, INC, Louisville, CO (US)
Filed on Apr. 5, 2021, as Appl. No. 17/222,122.
Application 17/222,122 is a continuation of application No. 15/930,098, filed on May 12, 2020, granted, now 10,972,321, issued on Apr. 6, 2021.
Application 15/930,098 is a continuation of application No. 16/391,061, filed on Apr. 22, 2019, granted, now 10,652,056, issued on May 12, 2020.
Application 16/391,061 is a continuation in part of application No. 16/288,057, filed on Feb. 27, 2019, granted, now 10,608,852, issued on Mar. 31, 2020.
Application 16/288,057 is a continuation in part of application No. 16/283,520, filed on Feb. 22, 2019, granted, now 10,601,510, issued on Mar. 24, 2020.
Application 16/283,520 is a continuation in part of application No. 16/191,315, filed on Nov. 14, 2018, granted, now 10,608,744, issued on Mar. 31, 2020.
Claims priority of provisional application 62/660,322, filed on Apr. 20, 2018.
Claims priority of provisional application 62/635,629, filed on Feb. 27, 2018.
Claims priority of provisional application 62/633,956, filed on Feb. 22, 2018.
Claims priority of provisional application 62/586,041, filed on Nov. 14, 2017.
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 25/49 (2006.01); H04W 88/08 (2009.01); H04B 10/2575 (2013.01); H03M 3/00 (2006.01); H04B 1/00 (2006.01)
CPC H04L 25/4906 (2013.01) [H03M 3/424 (2013.01); H03M 3/43 (2013.01); H03M 3/496 (2013.01); H04B 1/0007 (2013.01); H04W 88/085 (2013.01); H04B 10/2575 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A delta-sigma digitization interface for digitizing an input analog signal into a digitized bit stream, comprising: a sampling unit configured to sample the input analog signal at a predetermined sampling rate to produce a sampled analog signal; a segmentation unit configured to segment the sampled analog signal into a plurality of separate data pipelines; a delta-sigma analog-to-digital converter (ADC) having a processor and a memory, and wherein the memory contains computer-executable instructions that, when executed by the processor, cause the delta-sigma ADC to implement a delta-sigma algorithm configured to individually quantize a respective signal segment contained within each of the plurality of data pipelines into a digitized bit stream segment according to a predetermined number of quantization bits; a cascading unit configured to combine the respective quantized signal segments into a single digitized output stream; and an output port for transmitting the single digitized output stream to a transport medium as the digitized bit stream.
 
8. A delta-sigma digitization interface for digitizing an input analog signal into a digitized bit stream, comprising: a sampling unit configured to sample the input analog signal at a predetermined sampling rate to produce a sampled analog signal; a segmentation unit configured to segment and distribute contiguous data portions of the sampled analog signal in sequential order into a plurality of separate data pipelines, respectively; a delta-sigma analog-to-digital converter (ADC) configured to individually quantize a respective data portion contained within each of the plurality of data pipelines into a digitized bit stream segment according to a predetermined number of quantization bits; a cascading unit configured to combine the respective quantized signal segments into a single digitized output stream; and an output port for transmitting the single digitized output stream to a transport medium as the digitized bit stream.
 
18. A method of optimizing a delta-sigma analog-to-digital converter (ADC) architecture for a field programmable gate array (FPGA), comprising the steps of: simulating a performance of the delta-sigma ADC according to a first floating-point calculation using floating-point coefficients of the delta-sigma ADC; approximating key coefficients from a floating-point format to a fixed-point format; performing a second floating-point calculation of the delta-sigma ADC performance using the approximated key fixed-point coefficients; performing a first fixed-point calculation of the delta-sigma ADC performance for a continuous input data stream using fixed-point coefficients obtained from performance of the second floating-point calculation; and performing a second fixed-point calculation of the delta-sigma ADC performance, wherein the continuous input data stream is segmented into a plurality of separate data blocks, and wherein the second fixed-point calculation is individually performed on each separate segmented data block.