US 11,695,596 B2
Multi-level signal transmitter and method thereof
Ting-Hsu Chien, San Jose, CA (US); and Chia-Liang (Leon) Lin, Fremont, CA (US)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by Realtek Semiconductor Corp., Hsinchu (TW)
Filed on Apr. 19, 2021, as Appl. No. 17/233,597.
Prior Publication US 2022/0337458 A1, Oct. 20, 2022
Int. Cl. H04L 25/03 (2006.01); H04L 25/02 (2006.01); H04L 25/49 (2006.01)
CPC H04L 25/03114 (2013.01) [H04L 25/028 (2013.01); H04L 25/0272 (2013.01); H04L 25/4925 (2013.01); H04L 2025/03363 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A multi-level signal transmitter comprising:
an encoder figured to receive an input data and output a plurality of logical signal sets, each of said plurality of logical signal sets comprising a plurality of logical signals; and
a plurality of tree-structured drivers configured to receive said plurality of logical signal sets, respectively, and jointly establish an output voltage at an output node, wherein each of said tree-structure drivers comprises a plurality of inverters configured to receive said plurality of logical signals of its respective logical signal set and jointly establish a joint voltage at a bifurcation node via coupling to the bifurcation node through a plurality of first-level weighting resistors, and a second-level weighting resistor configured to couple the bifurcation node to the output node.