US 11,695,421 B1
Delay-locked loop, control method for delay-locked loop, and electronic device
Yinchuan Gu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jun. 2, 2022, as Appl. No. 17/805,091.
Application 17/805,091 is a continuation of application No. PCT/CN2022/085078, filed on Apr. 2, 2022.
Claims priority of application No. 202210043659.X (CN), filed on Jan. 14, 2022.
Int. Cl. H03L 7/081 (2006.01); H03L 7/085 (2006.01)
CPC H03L 7/0812 (2013.01) [H03L 7/085 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A delay-locked loop, comprising:
a secondary path configured to perform frequency division on an input clock signal to generate a frequency-divided clock signal, adjust the frequency-divided clock signal having a first frequency to obtain an output clock signal in a locking process of the delay-locked loop, and adjust the frequency-divided clock signal to make the frequency-divided clock signal have a second frequency when the delay-locked loop is locked in a standby state, wherein the second frequency is lower than the first frequency; and
a primary path configured to output, when obtaining a target instruction, an output clock replica signal having a same phase as the output clock signal.