US 11,695,420 B2
Logic-in-memory inverter using feedback field-effect transistor
Sang Sig Kim, Seoul (KR); Kyoung Ah Cho, Seoul (KR); Jae Min Son, Seongnam-si (KR); and Eun Woo Baek, Seoul (KR)
Assigned to Korea University Research and Business Foundation, Seoul (KR)
Filed by Korea University Research and Business Foundation, Seoul (KR)
Filed on Aug. 25, 2021, as Appl. No. 17/411,353.
Claims priority of application No. 10-2021-0088865 (KR), filed on Jul. 7, 2021.
Prior Publication US 2023/0012345 A1, Jan. 12, 2023
Int. Cl. H01L 29/739 (2006.01); H03K 19/017 (2006.01); H03K 19/00 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01)
CPC H03K 19/01714 (2013.01) [H01L 27/0922 (2013.01); H01L 29/0665 (2013.01); H03K 19/0013 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A logic-in-memory inverter comprising:
a metal oxide semiconductor field-effect transistor; and
a feedback field-effect transistor in which a drain region of a nanostructure is connected in series to a drain region of the metal oxide semiconductor field-effect transistor,
wherein the logic-in-memory inverter performs a logical operation based on an output voltage VOUT that changes depending on a level of an input voltage VIN that is input to a gate electrode of the feedback field-effect transistor and a gate electrode of the metal oxide semiconductor field-effect transistor while a source voltage VSS is input to a source region of the nanostructure and a drain voltage VDD is input to a source region of the metal oxide semiconductor field-effect transistor.