US 11,695,073 B2
Memory array gate structures
Chun-Chieh Lu, Taipei (TW); Sai-Hooi Yeong, Zhubei (TW); Bo-Feng Young, Taipei (TW); Yu-Ming Lin, Hsinchu (TW); and Chih-Yu Chang, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Oct. 16, 2020, as Appl. No. 17/72,367.
Claims priority of provisional application 63/031,730, filed on May 29, 2020.
Prior Publication US 2021/0376153 A1, Dec. 2, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); G11C 11/22 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H01L 29/04 (2006.01); H01L 29/66 (2006.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01)
CPC H01L 29/78391 (2014.09) [G11C 11/223 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); H01L 29/04 (2013.01); H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H10B 51/10 (2023.02); H10B 51/20 (2023.02); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory cell comprising:
a transistor over a semiconductor substrate, the transistor comprising:
a ferroelectric (FE) material directly contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal, wherein the word line is one of a plurality of vertically stacked word lines, and wherein the FE material directly contacts a respective sidewall of each of the plurality of vertically stacked word lines; and
an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line, and wherein the FE material further directly contacts the OS layer.