US 11,695,049 B2
High electron mobility transistor and method for forming the same
Chih-Tung Yeh, Taoyuan (TW); Chun-Liang Hou, Hsinchu County (TW); Wen-Jung Liao, Hsinchu (TW); Chun-Ming Chang, Kaohsiung (TW); Yi-Shan Hsu, Taipei (TW); and Ruey-Chyr Lee, Taichung (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Sep. 23, 2020, as Appl. No. 17/29,075.
Claims priority of application No. 202010799660.6 (CN), filed on Aug. 11, 2020.
Prior Publication US 2022/0052166 A1, Feb. 17, 2022
Int. Cl. H01L 29/417 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/205 (2006.01); H01L 29/20 (2006.01)
CPC H01L 29/4175 (2013.01) [H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/0684 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/401 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A high electron mobility transistor, comprising:
a substrate;
a mesa structure disposed on the substrate, wherein the mesa structure comprises a channel layer and a barrier layer on the channel layer;
a passivation layer disposed on the mesa structure;
at least a contact structure disposed in the passivation layer and the mesa structure, wherein the contact structure comprises a body portion and a plurality of protruding portions, the body portion penetrates through the passivation layer and a portion of the barrier layer, the plurality of protruding portions penetrate through the barrier layer and a portion of the channel layer, wherein a bottom surface of the body portion is lower than an upper surface of the barrier layer and higher than a bottom surface of the barrier layer; and
a gate structure disposed on the mesa structure and between the contact structure and another one of the contact structure, wherein the gate structure comprises:
a semiconductor gate layer directly disposed on the barrier layer of the mesa structure and covered by the passivation layer; and
a gate metal layer through the passivation layer to directly contact a top surface of the semiconductor gate layer.