	US 11,695,042 B2
	Transistor contacts and methods of forming the same
Wei-Ting Chien, Hsinchu (TW); Wen-Yen Chen, Hsinchu (TW); Li-Ting Wang, Hsinchu (TW); Su-Hao Liu, Jhongpu Township (TW); Liang-Yin Chen, Hsinchu (TW); and Huicheng Chang, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 10, 2021, as Appl. No. 17/344,049.
Claims priority of provisional application 63/172,357, filed on Apr. 8, 2021.
Prior Publication US 2022/0328631 A1, Oct. 13, 2022
Int. Cl. H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/3115 (2006.01); H01L 21/768 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01)

CPC H01L 29/1054 (2013.01) [H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01)]

20 Claims

1. A method comprising:

depositing an inter-layer dielectric on a source/drain region;

forming a gate mask on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region;

implanting an impurity in the gate mask to increase an etching selectivity between the gate mask and the inter-layer dielectric relative a contact etching process; and

performing the contact etching process to pattern a contact opening in the inter-layer dielectric, the contact opening exposing the source/drain region, the gate mask covering the gate structure during the contact etching process, a protective layer being formed on the gate mask during the contact etching process, the protective layer comprising a polymer byproduct of the contact etching process.