CPC H01L 27/098 (2013.01) [H01L 23/52 (2013.01); H01L 29/0615 (2013.01); H01L 29/0696 (2013.01)] | 20 Claims |
1. An integrated circuit layout cell comprising:
a doped region of a first conductivity type;
a doped region of a second conductivity type opposite of the first conductivity type;
a further doped region of the first conductivity type at least partially within the doped region of the second conductivity type, and continuous with the doped region of the first conductivity type;
a first transistor having a control terminal, a first controlled terminal, and a second controlled terminal, the first controlled terminal and the second controlled terminal of the first transistor comprising terminal regions of the second conductivity type formed within the further doped region of the first conductivity type;
a second transistor having a control terminal, a first controlled terminal, and a second controlled terminal, the first controlled terminal and the second controlled terminal of the second transistor comprising terminal regions of the first conductivity type;
wherein the first controlled terminal of the first transistor is in electrical connection with the first controlled terminal of the second transistor; and
wherein the second controlled terminal of the first transistor is in electrical connection with the second controlled terminal of the second transistor.
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