US 11,694,993 B2
Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same
Weihua Cheng, Wuhan (CN); and Jun Liu, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Oct. 12, 2021, as Appl. No. 17/499,134.
Application 17/499,134 is a continuation of application No. 16/669,450, filed on Oct. 30, 2019, granted, now 11,158,604.
Application 16/669,450 is a continuation of application No. PCT/CN2019/105292, filed on Sep. 11, 2019.
Claims priority of application No. PCT/CN2019/082607 (WO), filed on Apr. 15, 2019; application No. PCT/CN2019/085237 (WO), filed on Apr. 30, 2019; and application No. PCT/CN2019/097442 (WO), filed on Jul. 24, 2019.
Prior Publication US 2022/0028829 A1, Jan. 27, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/18 (2023.01); H01L 25/065 (2023.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 21/78 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first semiconductor structure comprising an array of NAND memory cells, a first semiconductor layer above and in contact with the array of NAND memory cells, and a first bonding layer comprising a plurality of first bonding contacts, the array of NAND memory cells being above the first bonding layer;
a second semiconductor structure comprising an array of dynamic random-access memory (DRAM) cells and a second bonding layer comprising a plurality of second bonding contacts; and
a third semiconductor structure comprising a substrate, a processor on the substrate, an array of static random-access memory (SRAM) cells on the substrate and outside of the processor, and a third bonding layer above the processor and the array of SRAM cells, the third bonding layer comprising a plurality of third bonding contacts,
wherein the first bonding layer is above the third bonding layer,
the first bonding contacts are in contact with a first set of the third bonding contacts, and
the second bonding contacts are in contact with a second set of the third bonding contacts.