US 11,694,983 B2
Test pad structure of chip
Kuo-Wei Tseng, Jhubei (TW); and Po-Chi Chen, Jhubei (TW)
Assigned to Sitronix Technology Corporation, Jhubei (TW)
Filed by SITRONIX TECHNOLOGY CORP., Jhubei (TW)
Filed on Aug. 2, 2021, as Appl. No. 17/444,233.
Claims priority of provisional application 63/059,178, filed on Jul. 31, 2020.
Prior Publication US 2022/0037218 A1, Feb. 3, 2022
Int. Cl. H01L 23/58 (2006.01); H01L 23/00 (2006.01); H01L 21/66 (2006.01)
CPC H01L 24/13 (2013.01) [H01L 22/32 (2013.01); H01L 24/06 (2013.01); H01L 24/14 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/10145 (2013.01); H01L 2224/13013 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/14051 (2013.01); H01L 2224/14133 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A test pad structure of chip, comprising:
a plurality of first internal test pads, disposed in a chip;
a plurality of second internal test pads, disposed in said chip, and spaced with said first internal test pads by a distance;
a plurality of first extended test pads, disposed on said chip, connected with said first internal test pads, and located above said first internal test pads; and
a plurality of second extended test pads, disposed on said chip, connected with said second internal test pads, and located above said second internal test pads;
wherein said first and second extended test pads transmit signals or power to said first and second internal test pads.