US 11,694,975 B2
Chip package structure
Jiun-Ting Chen, Hsinchu (TW); Ying-Ching Shih, Hsinchu (TW); Szu-Wei Lu, Hsinchu (TW); and Chih-Wei Wu, Zhuangwei Township, Yilan County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 3, 2021, as Appl. No. 17/392,868.
Application 17/392,868 is a division of application No. 16/395,385, filed on Apr. 26, 2019, granted, now 11,088,086.
Prior Publication US 2021/0366842 A1, Nov. 25, 2021
Int. Cl. H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/563 (2013.01); H01L 23/3157 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip package structure, comprising:
a substrate;
a first chip structure and a second chip structure over the substrate; and
an anti-warpage bar over a first portion of the first chip structure and over a second portion of the second chip structure, wherein a width of the anti-warpage bar overlapping the second portion of the second chip structure is greater than a width of the anti-warpage bar overlapping the first portion of the first chip structure, wherein a bottom surface of the anti-warpage bar is at a level between a top surface of the second chip structure and a bottom surface of the second chip structure.