US 11,694,968 B2
Three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate
Seok Won Cho, Watervliet, NY (US); Ki-Il Kim, Clifton Park, NY (US); and Kang Ill Seo, Springfield, VA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD, Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 25, 2021, as Appl. No. 17/157,374.
Claims priority of provisional application 63/113,626, filed on Nov. 13, 2020.
Prior Publication US 2022/0157737 A1, May 19, 2022
Int. Cl. H01L 23/544 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/544 (2013.01) [H01L 23/481 (2013.01); H01L 24/83 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/8313 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor architecture comprising:
a carrier substrate;
alignment marks provided in the carrier substrate, the alignment marks being provided from a first surface of the carrier substrate to a second surface of the carrier substrate;
a first semiconductor device provided on the first surface of the carrier substrate based on the alignment marks, the first semiconductor device comprising a buried power rail (BPR) that is extended in a horizontal direction, and formed at an active device level different from metal interconnect structures; and
a second semiconductor device provided on the second surface of the carrier substrate based on the alignment marks and aligned with the first semiconductor device,
wherein a through-silicon via (TSV) penetrates through the carrier substrate in a vertical direction, perpendicular to the horizontal direction, and contacts the BPR and the second semiconductor device.