US 11,694,944 B1
3D semiconductor device and structure with metal layers and a connective path
Zvi Or-Bach, Haifa (IL); Deepak C. Sekar, Sunnyvale, CA (US); and Brian Cronquist, Klamath Falls, OR (US)
Assigned to Monolithic 3D Inc., Klamath Falls, OR (US)
Filed by Monolithic 3D Inc., Klamath Falls, OR (US)
Filed on Feb. 13, 2023, as Appl. No. 18/109,254.
Application 18/109,254 is a continuation in part of application No. 18/070,422, filed on Nov. 28, 2022, granted, now 11,616,004.
Application 18/070,422 is a continuation in part of application No. 17/941,891, filed on Sep. 9, 2022, granted, now 11,594,473, issued on Feb. 28, 2023.
Application 17/941,891 is a continuation in part of application No. 17/850,819, filed on Jun. 27, 2022, granted, now 11,476,181, issued on Oct. 18, 2022.
Application 17/850,819 is a continuation in part of application No. 17/492,577, filed on Oct. 2, 2021, granted, now 11,410,912, issued on Aug. 9, 2022.
Application 17/492,577 is a continuation in part of application No. 17/313,986, filed on May 6, 2021, granted, now 11,164,811, issued on Nov. 2, 2021.
Application 17/313,986 is a continuation in part of application No. 16/852,506, filed on Apr. 19, 2020, granted, now 11,088,050, issued on Aug. 10, 2021.
Application 16/852,506 is a continuation in part of application No. 16/536,606, filed on Aug. 9, 2019, granted, now 10,665,695, issued on May 26, 2020.
Application 16/536,606 is a continuation in part of application No. 16/004,404, filed on Jun. 10, 2018, granted, now 10,600,888, issued on Mar. 24, 2020.
Application 16/004,404 is a continuation in part of application No. 15/917,629, filed on Mar. 10, 2018, granted, now 10,038,073, issued on Jul. 13, 2018.
Application 15/917,629 is a continuation in part of application No. 15/622,124, filed on Jun. 14, 2017, granted, now 9,954,080, issued on Apr. 24, 2018.
Application 15/622,124 is a continuation in part of application No. 14/880,276, filed on Oct. 11, 2015, granted, now 9,691,869, issued on Jun. 14, 2017.
Application 14/880,276 is a continuation in part of application No. 14/472,108, filed on Aug. 28, 2014, granted, now 9,305,867, issued on Apr. 5, 2016.
Application 14/472,108 is a continuation of application No. 13/959,994, filed on Aug. 6, 2013, granted, now 8,836,073, issued on Sep. 25, 2014.
Application 13/959,994 is a continuation of application No. 13/441,923, filed on Apr. 9, 2012, granted, now 8,557,632, issued on Oct. 15, 2013.
Int. Cl. H01L 23/48 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 29/732 (2006.01); H01L 27/118 (2006.01); H01L 29/10 (2006.01); H01L 29/808 (2006.01); H01L 29/66 (2006.01); H01L 27/02 (2006.01); H01L 29/78 (2006.01); H01L 21/74 (2006.01); H10B 12/00 (2023.01); H10B 41/20 (2023.01); H10B 41/40 (2023.01); H10B 43/20 (2023.01); H10B 43/40 (2023.01); H01L 23/544 (2006.01); H01L 23/34 (2006.01); H01L 23/50 (2006.01); H10B 63/00 (2023.01)
CPC H01L 23/481 (2013.01) [H01L 21/743 (2013.01); H01L 23/34 (2013.01); H01L 23/50 (2013.01); H01L 23/544 (2013.01); H01L 27/0207 (2013.01); H01L 27/0688 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H01L 27/11807 (2013.01); H01L 29/1066 (2013.01); H01L 29/66272 (2013.01); H01L 29/66704 (2013.01); H01L 29/66825 (2013.01); H01L 29/66901 (2013.01); H01L 29/732 (2013.01); H01L 29/7841 (2013.01); H01L 29/808 (2013.01); H10B 12/09 (2023.02); H10B 12/20 (2023.02); H10B 12/50 (2023.02); H10B 41/20 (2023.02); H10B 41/40 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02); H01L 27/0623 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/16152 (2013.01); H10B 63/30 (2023.02); H10B 63/845 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A 3D semiconductor device, the device comprising:
a first level comprising a plurality of first metal layers;
a second level,
wherein said second level overlays said first level,
wherein said second level comprises at least one single crystal silicon layer,
wherein said second level comprises a plurality of transistors,
wherein each transistor of said plurality of transistors comprises a single crystal channel,
wherein said second level comprises a plurality of second metal layers,
wherein said plurality of second metal layers comprise interconnections between said transistors of said plurality of transistors, and
wherein said second level is overlaid by a first isolation layer; and
a connective path between said plurality of transistors and said plurality of first metal layers,
wherein said connective path comprises a via disposed through at least said single crystal silicon layer, and
wherein said via comprises contact with at least one of said plurality of transistors.