	US 11,694,932 B2
	Array of vertical transistors, an array of memory cells comprising an array of vertical transistors, and a method used in forming an array of vertical transistors
Marcello Calabrese, Monza (IT); Antonino Rigano, Cernusco sul Naviglio (IT); and Marcello Mariani, Milan (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 16, 2022, as Appl. No. 17/745,338.
Application 17/745,338 is a continuation of application No. 17/023,142, filed on Sep. 16, 2020, granted, now 11,373,914.
Claims priority of provisional application 63/071,141, filed on Aug. 27, 2020.
Prior Publication US 2022/0278001 A1, Sep. 1, 2022
Int. Cl. H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H10B 51/30 (2023.01)

CPC H01L 21/823487 (2013.01) [H01L 21/02236 (2013.01); H01L 21/823418 (2013.01); H01L 21/823462 (2013.01); H01L 21/823475 (2013.01); H01L 29/40111 (2019.08); H01L 29/6684 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 29/78391 (2014.09); H10B 51/30 (2023.02)]

27 Claims

1. A vertical transistor comprising:

an upper source/drain region, a channel region, and a lower source/drain region; the channel region comprising an upper portion, an intervening portion, and a lower portion;

insulative material along a sidewall of the channel region, a sidewall of the upper source/drain region, and a sidewall of the lower source/drain region;

conductive material adjacent the insulative material, the conductive material vertically extending from a level corresponding to an upper portion of the lower source/drain region to a level corresponding to a lower portion of the upper source/drain region; and

the insulative material being thicker at both the level corresponding to the upper portion of the lower source/drain region and the level corresponding to the lower portion of the upper source/drain region than at a level corresponding to the intervening portion of the channel region.