US 11,694,926 B2
Barrier free interface between beol interconnects
Hsiu-Wen Hsueh, Taichung (TW); Chii-Ping Chen, Hsinchu (TW); Po-Hsiang Huang, Taipei (TW); and Ya-Ching Tseng, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Sep. 25, 2020, as Appl. No. 17/32,407.
Claims priority of provisional application 63/015,799, filed on Apr. 27, 2020.
Prior Publication US 2021/0335663 A1, Oct. 28, 2021
Int. Cl. H01L 21/768 (2006.01); H01L 23/535 (2006.01)
CPC H01L 21/76844 (2013.01) [H01L 21/7684 (2013.01); H01L 21/76805 (2013.01); H01L 21/76834 (2013.01); H01L 21/76846 (2013.01); H01L 21/76849 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a first interconnect disposed between lower sidewalls of an inter-level dielectric (ILD) structure over a substrate, the first interconnect having sidewalls that contact the lower sidewalls of the ILD structure along interfaces as viewed along a cross-sectional view;
a barrier layer disposed along upper sidewalls of the ILD structure and having sidewalls defining an opening over the first interconnect;
a second interconnect disposed on the barrier layer, wherein the second interconnect extends through the opening in the barrier layer and to the first interconnect and wherein a bottommost surface of the barrier layer laterally extends past an interior sidewall of the barrier layer that faces the second interconnect; and
wherein opposing outermost edges of a bottommost surface of the second interconnect are laterally aligned with the interfaces.