US 11,694,901 B2
Field-effect transistor and method for manufacturing the same
Qiuxia Xu, Shanghai (CN); and Kai Chen, Shanghai (CN)
Assigned to Shanghai Industrial μTechnology Research Institute, Shanghai (CN)
Filed by Shanghai Industrial μTechnology Research Institute, Shanghai (CN)
Filed on Jul. 9, 2021, as Appl. No. 17/371,142.
Application 17/371,142 is a continuation of application No. 16/822,175, filed on Mar. 18, 2020, granted, now 11,217,694.
Claims priority of application No. 201910202715.8 (CN), filed on Mar. 18, 2019; application No. 201910202716.2 (CN), filed on Mar. 18, 2019; and application No. 201910202930.8 (CN), filed on Mar. 18, 2019.
Prior Publication US 2021/0343544 A1, Nov. 4, 2021
Int. Cl. H01L 21/3065 (2006.01); H01L 21/3213 (2006.01); H01L 29/49 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01)
CPC H01L 21/30655 (2013.01) [H01L 21/02603 (2013.01); H01L 21/28238 (2013.01); H01L 21/32139 (2013.01); H01L 29/0669 (2013.01); H01L 29/42372 (2013.01); H01L 29/42392 (2013.01); H01L 29/49 (2013.01); H01L 29/78391 (2014.09)] 28 Claims
OG exemplary drawing
 
1. A method for manufacturing a field-effect transistor, comprising:
forming an NMOSFET region and a PMOSFET region on a substrate, wherein the NMOSFET region and the PMOSFET region are separated by shallow trench isolation; and
forming a hard mask on the NMOSFET region and the PMOSFET region, and patterning through the hard mask; and
forming a multiple of stacked nanowires in the NMOSFET region and a multiple of stacked nanowires in the PMOSFET region by:
performing repeated alternating anisotropic and isotropic plasma etching in the NMOSFET region and the PMOSFET region; and
forming a passivation film by oxidizing the surface of each of the exposed nanowires by plasma after each step of etching,
wherein the passivation film has a portion located on the surface of the substrate in the NMOSFET region and the PMOSFET region and the portion is removed by anisotropic plasma to facilitate the subsequent etching; and
processing the multiple of stacked nanowires in the NMOSFET region to form a first array of nanowires in the NMOSFET region and processing the multiple of stacked nanowires in the PMOSFET region to form a second array of nanowires in the PMOSFET region; and
forming an interfacial oxide layer, a ferroelectric layer, and a stacked metal gate in sequence around each of the nanowires included in the first array and the second array.