US 11,694,747 B2
Self-selecting memory cells configured to store more than one bit per memory cell
Lingming Yang, Meridian, ID (US); Xuan Anh Tran, Irvine, CA (US); Karthik Sarpatwari, Boise, ID (US); Francesco Douglas Verna-Ketel, Boise, ID (US); Jessica Chen, Boise, ID (US); Nevil N. Gajera, Meridian, ID (US); and Amitava Majumdar, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 3, 2021, as Appl. No. 17/337,806.
Prior Publication US 2022/0392526 A1, Dec. 8, 2022
Int. Cl. G11C 13/00 (2006.01); G11C 11/56 (2006.01)
CPC G11C 11/5678 (2013.01) [G11C 13/0004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01); G11C 2013/0092 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A device, comprising:
memory cells;
voltage drivers connected to the memory cells; and
a controller coupled to the voltage drivers;
wherein, in response to a determination to program a threshold voltage of a memory cell to a level representative of a value, the controller is configured to instruct the voltage drivers to:
drive a first voltage pulse across the memory cell to cause a predetermined current to go through the memory cell; and
drive a second voltage pulse, different from the first voltage pulse and within a time period that is no more than one tenth of a duration of the first voltage pulse, across the memory cell.